During deposition of metal on a semiconductor wafer, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), electro-chemical plating (ECP), or electroless plating (ELP), improper fill or voids may be formed in vias or trenches due to various factors such as improper mass transport, reaction kinetics, a contaminated substrate, etc. The presence of a buried void in a semiconductor wafer, e.g., in a trench silicide structure, may cause serious reliability concerns. However, buried voids cannot currently be detected by surface scans, e.g., bright field inspection (BFI), scanning electron microscope (SEM), etc. In addition, inspection of a wafer by electron beam (Ebeam) is also challenging. Such defects are currently only highlighted post-production by failure analysis (FA) cuts of the wafer or by electrical test (ET) data showing either open or increased contact resistance.
A need therefore exists for methodology and an apparatus enabling detection of buried voids in a semiconductor wafer inline post metal deposition.